`include "common_header.verilog"

//  *************************************************************************
//  File : p8264_first_am_detect.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2008 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Denis Poverennyy
//  info@morethanip.com
//  *************************************************************************
//  Description : 40G PCS Alignment Marker Detection
//  First Marker Detect module searches for an Alignment Marker one time after reset. 
//  As soon as a first Alignment Marker is found, the First Marker Detect block signals
//   "marker detected" (marker_det) and stops searching procedure. 
//  Version     : $Id: p8264_first_am_detect.v,v 1.2 2014/10/09 14:58:07 dk Exp $
//  *************************************************************************

module p8264_first_am_detect (
        reset,
        clk,
        data_val,
        block_lock,
        sw_reset,
        data_in,
        sh_in,
        vl_0_enc,
        vl_1_enc,
        vl_2_enc,
        vl_3_enc,        
        marker_det,
        vl_match_num);

input                   reset;          // async active high reset
input                   clk;            // system clock
input                   data_val;       // Data and Sync header valid
input                   block_lock;     // Lock state reached
input                   sw_reset;       // Software reset
input   [63:0]          data_in;        // Data input
input   [1:0]           sh_in;          // Sync header
input   [23:0]          vl_0_enc;       // Marker pattern for PCS Virtual Lane 0
input   [23:0]          vl_1_enc;       // Marker pattern for PCS Virtual Lane 1
input   [23:0]          vl_2_enc;       // Marker pattern for PCS Virtual Lane 2
input   [23:0]          vl_3_enc;       // Marker pattern for PCS Virtual Lane 3

output                  marker_det;     // any alignment marker detected
output   [3:0]          vl_match_num;   // marker's number detected 


//-------------------------------------
// Output Signals
//-------------------------------------
wire            marker_det; 
wire    [3:0]   vl_match_num; 

//-------------------------------------
// Internal Signals
//-------------------------------------
wire                    marker_det_int; //  the same as marker_det
wire    [3:0]           vl_match; //  the same as  vl_match_num
wire    [24*4 -1: 0]    vl_enc = {vl_3_enc, vl_2_enc, vl_1_enc, vl_0_enc};


 
assign marker_det_int = vl_match[3] | vl_match[2] | vl_match[1] | vl_match[0]; 
assign marker_det = marker_det_int; 
assign vl_match_num = {vl_match[3], vl_match[2], vl_match[1], vl_match[0]}; 



genvar gi;
generate for(gi=0; gi< 4; gi=gi+1)
begin:gen_am_latch
        


marker_latch U_MARKER_LATCH (
        .reset                  (reset),
        .clk                    (clk),
        .data_val               (data_val),
        .block_lock             (block_lock),
        .sw_reset               (sw_reset),
        .data_in                (data_in),
        .sh_in                  (sh_in),
        .marker_det             (marker_det_int),
        .vl_enc                 (vl_enc[gi * 24 + 24 -1 :gi * 24]),
        .vl_match               (vl_match[gi]));
end
endgenerate


















endmodule // module p8264_first_am_detect

